Electrical
Engineering Department
EExxx VLSI Design Laboratory
Lab 1: Design
rule checking and Circuit layout
Lab 2: Layout
of 2 inputs Nand Gate and Concept of Parasitic extraction
Lab 3: Layout
of 2-1 and 4-1 multiplexers
Lab 4: Cell
Manipulation in Layout
Lab 5: Schematic
Editor S-Edit_ Standard Cells
Lab 6: Placement
and Routing part (I)
Lab 7: Placement
and Routing part (II)
Lab 8: Layout
of Arithmetic Circuits: Half and Full Adder/Subtractor
Lab 9: Layout
of Two-bit binary CMOS multiplier circuit
Midterm exam
Lab 10:
Layout of State Machines
Lab 11: Layout of 3-bit Parallel
Register
Lab 12: Layout of parallel
To Serial Data Conversion
Lab 13: Introduction to Maxplus II
Project
presentation